Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores

TL;DR

This paper proposes the design of vector coprocessors for multi-threaded RISC-V cores to enhance energy efficiency and performance in computation-heavy edge applications like AI and signal processing.

Contribution

It introduces a vector coprocessing approach tailored for IMT RISC-V cores, combining multi-threading and data-level parallelism for improved workload acceleration.

Findings

Enhanced energy efficiency in edge computing workloads

Effective integration of vector units with IMT cores

Potential for reduced hardware costs and increased performance

Abstract

Computation intensive kernels, such as convolutions, matrix multiplication and Fourier transform, are fundamental to edge-computing AI, signal processing and cryptographic applications. Interleaved-Multi-Threading (IMT) processor cores are interesting to pursue energy efficiency and low hardware cost for edge-computing, yet they need hardware acceleration schemes to run heavy computational workloads. Following a vector approach to accelerate computations, this study explores possible alternatives to implement vector coprocessing units in RISC-V cores, showing the synergy between IMT and data-level parallelism in the target workloads.