Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function

TL;DR

This paper analyzes the security of arbiter-based physical unclonable functions (PUFs) by modeling machine learning attacks, specifically logistic regression, and validates the design on FPGA hardware.

Contribution

It introduces a modified APUF design and evaluates its resistance against ML-based attacks, extending prior work on PUF security analysis.

Findings

ML attacks successfully compromise existing APUF designs

The modified APUF shows improved resistance to logistic regression attacks

Validation on FPGA confirms practical applicability

Abstract

This paper deals with study of the physical unclonable functions and specifically the design of arbiter based PUF (APUF) and extends the work on different types of attacks on the PUF designs to break the security of the device, which includes advanced computational algorithms. Machine learning (ML) based attacks are successful in attacking existing designs. So in this, the resistance of the modified, proposed design of APUF is examined by modelling the attack based on the logistic regression a MLbased algorithm. The design is validated on Basys-3 Artix -7 FPGA board with a part number (xc7a35tcpg236-1).