Spin-Hall MTJ Cells for Intra-Column Competition in Hierarchical Temporal Memory

TL;DR

This paper introduces a spin-Hall magnetoresistive memory cell circuit for efficient intra-column competition in Hierarchical Temporal Memory, leveraging memristors and spintronic devices for fast, low-power operation.

Contribution

It presents a novel spintronic winner-take-all circuit with memristors for HTM, enabling rapid and energy-efficient intra-column competition simulation.

Findings

Circuit completes 9-cell competition in under 15 ns

Energy consumption is approximately 25 pJ per operation

Simulations validate the circuit's performance and compatibility with CMOS

Abstract

We propose a dedicated winner-take-all circuit to efficiently implement the intra-column competition between cells in Hierarchical Temporal Memory which is a crucial part of the algorithm. All inputs and outputs are charge-based for compatibility with standard CMOS. The circuit incorporates memristors for competitive advantage to emulate a column with a cell in a predictive state. The circuit can also detect columns 'bursting' by passive averaging and comparison of the cell outputs. The proposed spintronic devices and circuit are thoroughly described and a series of simulations are used to predict the performance. The simulations indicate that the circuit can complete a nine-cell, nine-input competition operation in under 15 ns at a cost of about 25 pJ.