Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled-S gate

TL;DR

This paper demonstrates the calibration and benchmarking of a non-Clifford controlled-S gate on IBM Quantum hardware, achieving low error rates close to the coherence limit using interleaved randomized benchmarking.

Contribution

It introduces a method for calibrating a non-Clifford two-qubit gate and measures its error using a specialized benchmarking technique, showing improved performance over standard gates.

Findings

Achieved a gate error of approximately 0.0059.

The calibrated CS gate's error is close to the qubits' coherence limit.

The non-Clifford gate outperforms the standard CNOT gate in error rate.

Abstract

Hardware efficient transpilation of quantum circuits to a quantum devices native gateset is essential for the execution of quantum algorithms on noisy quantum computers. Typical quantum devices utilize a gateset with a single two-qubit Clifford entangling gate per pair of coupled qubits, however, in some applications access to a non-Clifford two-qubit gate can result in more optimal circuit decompositions and also allows more flexibility in optimizing over noise. We demonstrate calibration of a low error non-Clifford Controlled-$\frac{\pi}{2}$ phase (CS) gate on a cloud based IBM Quantum computing using the Qiskit Pulse framework. To measure the gate error of the calibrated CS gate we perform non-Clifford CNOT-Dihedral interleaved randomized benchmarking. We are able to obtain a gate error of $5.9(7) \times 10^{-3}$ at a gate length 263 ns, which is close to the coherence limit of the associated qubits, and lower error than the backends standard calibrated CNOT gate.