Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)

TL;DR

This paper introduces an area-efficient VLSI implementation of a finite field multiplier using a novel serial-in parallel-out algorithm with interleaved modular reduction, optimized for logic resource usage.

Contribution

It presents a new modified multiplication algorithm with interleaved reduction that reduces complexity and improves area efficiency over existing methods.

Findings

Outperforms previous algorithms in area efficiency

Uses fewer logic NAND gates for implementation

Achieves reduced latency and gate-latch count

Abstract

Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known results