A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22$\%$ INL

TL;DR

This paper presents a low-power, highly-linear phase interpolator with constant-slope operation, powered by an LDO, achieving superior INL and energy efficiency for clock generation in IoT systems.

Contribution

It introduces a novel constant-slope phase interpolator powered by an LDO, offering improved linearity and energy efficiency over existing digital-to-time converters.

Findings

Achieves 0.22% INL, significantly better than state-of-the-art PIs.

Consumes only 350μW at 0.5GHz, outperforming digital-to-time converters in energy efficiency.

Operates effectively with a 1.2V supply in 65-nm CMOS technology.

Abstract

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e. phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a low-dropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350$\mu$W at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4$\times$-15$\times$ lower than state-of-the-art (SoA) digital-to-time converters (DTCs) and an integral non-linearity (INL) of 2.5$\times$-3.1$\times$ better than SoA PIs, striking a good balance between linearity and energy efficiency.