2D Qubit Placement of Quantum Circuits using LONGPATH

TL;DR

This paper proposes two algorithms to optimize qubit placement in quantum circuits, significantly reducing SWAP gates needed for physical implementation on 2D grids, thereby improving efficiency.

Contribution

It introduces novel algorithms for qubit placement that minimize SWAP gates in 2D quantum architectures, enhancing quantum circuit synthesis.

Findings

Significant reduction in SWAP gates for 1D and 2D architectures.

Improved efficiency in quantum circuit physical synthesis.

Algorithms applicable to arbitrary quantum circuits.

Abstract

In order to achieve speedup over conventional classical computing for finding solution of computationally hard problems, quantum computing was introduced. Quantum algorithms can be simulated in a pseudo quantum environment, but implementation involves realization of quantum circuits through physical synthesis of quantum gates. This requires decomposition of complex quantum gates into a cascade of simple one qubit and two qubit gates. The methodological framework for physical synthesis imposes a constraint regarding placement of operands (qubits) and operators. If physical qubits can be placed on a grid, where each node of the grid represents a qubit then quantum gates can only be operated on adjacent qubits, otherwise SWAP gates must be inserted to convert non-Linear Nearest Neighbor architecture to Linear Nearest Neighbor architecture. Insertion of SWAP gates should be made optimal to reduce cumulative cost of physical implementation. A schedule layout generation is required for placement and routing apriori to actual implementation. In this paper, two algorithms are proposed to optimize the number of SWAP gates in any arbitrary quantum circuit. The first algorithm is intended to start with generation of an interaction graph followed by finding the longest path starting from the node with maximum degree. The second algorithm optimizes the number of SWAP gates between any pair of non-neighbouring qubits. Our proposed approach has a significant reduction in number of SWAP gates in 1D and 2D NTC architecture.