A CMOS-compatible Ising Machine with Bistable Nodes

TL;DR

This paper introduces a CMOS-compatible Ising machine design using bistable nodes, offering competitive solution quality with faster execution and lower energy consumption for chip-scale optimization tasks.

Contribution

It presents a novel integrated electronic Ising machine with bistable nodes, enabling efficient, scalable, and CMOS-compatible solutions for combinatorial optimization.

Findings

Competitive solution quality demonstrated

Significantly faster execution time

Lower energy consumption compared to existing designs

Abstract

Physical Ising machines rely on nature to guide a dynamical system towards an optimal state which can be read out as a heuristical solution to a combinatorial optimization problem. Such designs that use nature as a computing mechanism can lead to higher performance and/or lower operation costs and hence have attracted research and prototyping efforts from industry and academia. Quantum annealers are a prominent example of such efforts. However, some physics-centric Ising machines require stringent operating conditions that result in significant bulk and energy budget. Such disadvantages may be acceptable if these designs provide some significant intrinsic advantages at a much larger scale in the future, which remains to be seen. But for now, integrated electronic designs of Ising machines allow more immediate applications. We propose one such design that uses bistable nodes, coupled with programmable and variable strengths. The design is fully CMOS compatible for chip-scale applications and demonstrates competitive solution quality and significantly superior execution time and energy.