Embracing the Unreliability of Memory Devices for Neuromorphic Computing

TL;DR

This paper proposes a brain-inspired hybrid CMOS/RRAM memory architecture for neuromorphic computing that tolerates device unreliability without traditional error correction, enabling energy-efficient neural network implementation.

Contribution

It introduces a differential hybrid CMOS/RRAM architecture designed for neural networks that operates reliably despite device unreliability without using ECC.

Findings

Low-energy programming slightly reduces network accuracy

The architecture functions effectively without formal ECC

Device unreliability can be managed in neuromorphic systems

Abstract

The emergence of resistive non-volatile memories opens the way to highly energy-efficient computation near- or in-memory. However, this type of computation is not compatible with conventional ECC, and has to deal with device unreliability. Inspired by the architecture of animal brains, we present a manufactured differential hybrid CMOS/RRAM memory architecture suitable for neural network implementation that functions without formal ECC. We also show that using low-energy but error-prone programming conditions only slightly reduces network accuracy.