The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform

TL;DR

This paper introduces a blockchain-based hardware architecture that securely logs the entire life cycle of secret keys, preventing misuse and ensuring integrity in cryptographic systems.

Contribution

It presents the first hardware platform integrating blockchain technology to cryptographically log secret key life cycle events, enhancing security and auditability.

Findings

Successfully implemented on FPGA with nominal resource overhead.

Ensured secret keys never enter processor area during crypto operations.

Achieved cryptographic logging of key life cycle with authentication.

Abstract

The growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data make it more important to keep secret keys safe and secure. Few major issues on secret keys like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and non-destruction of keys can compromise the whole security system dangerously. In this article, we have proposed and implemented an isolated secret key memory which can log life cycle of secret keys cryptographically using blockchain (BC) technology. We have also implemented a special custom bus interconnect which receives custom crypto instruction from Processing Element (PE). During the execution of crypto instructions, the architecture assures that secret key will never come in the processor area and the movement of secret keys to various crypto core is recorded cryptographically after the proper authentication process controlled by proposed hardware based BC. To the best of our knowledge, this is the first work which uses blockchain based solution to address the issues of the life cycle of the secret keys in hardware platform. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is very nominal. We have used Xilinx Vivado EDA tool and Artix 7 FPGA board.