Quantum Fan-out: Circuit Optimizations and Technology Modeling

TL;DR

This paper introduces circuit optimizations and new memory architectures leveraging global interactions for fan-out in quantum computing, demonstrating potential runtime improvements and error reduction on NISQ devices.

Contribution

It presents a novel approach to circuit synthesis and memory design using fan-out enabled by global interactions, with experimental validation and realistic simulations.

Findings

Asymptotic runtime advantage shown in simulations

7-24% error reduction in NISQ circuits

Experimental proof-of-concept with superconducting qubits

Abstract

Instruction scheduling is a key compiler optimization in quantum computing, just as it is for classical computing. Current schedulers optimize for data parallelism by allowing simultaneous execution of instructions, as long as their qubits do not overlap. However, on many quantum hardware platforms, instructions on overlapping qubits can be executed simultaneously through __global interactions__. For example, while fan-out in traditional quantum circuits can only be implemented sequentially when viewed at the logical level, global interactions at the physical level allow fan-out to be achieved in one step. We leverage this simultaneous fan-out primitive to optimize circuit synthesis for NISQ (Noisy Intermediate-Scale Quantum) workloads. In addition, we introduce novel quantum memory architectures based on fan-out. Our work also addresses hardware implementation of the fan-out primitive. We perform realistic simulations for trapped ion quantum computers. We also demonstrate experimental proof-of-concept of fan-out with superconducting qubits. We perform depth (runtime) and fidelity estimation for NISQ application circuits and quantum memory architectures under realistic noise models. Our simulations indicate promising results with an asymptotic advantage in runtime, as well as 7--24% reduction in error.