Simulation-Guided Boolean Resubstitution

TL;DR

This paper introduces a simulation-guided Boolean resubstitution method that significantly reduces circuit size by leveraging circuit simulation instead of traditional Boolean reasoning, demonstrating up to 74% improvement.

Contribution

It presents a novel logic optimization approach based on circuit simulation, reducing reliance on SAT-solving and BDD construction, with effective pattern generation and filtering techniques.

Findings

Achieved up to 74% circuit size reduction

Developed highly expressive simulation patterns

Reduced need for SAT validation in resubstitution

Abstract

This paper proposes a new logic optimization paradigm based on circuit simulation, which reduces the need for Boolean computations such as SAT-solving or constructing BDDs. The paper develops a Boolean resubstitution framework to demonstrate the effectiveness of the proposed approach. Methods to generate highly expressive simulation patterns are developed, and the generated patterns are used in resubstitution for efficient filtering of potential resubstitution candidates to reduce the need for SAT validation. Experimental results show that improvements in circuit size reduction were achieved by up to 74%, compared to a state-of-the-art resubstitution algorithm.