Insight into Potential Well Based Nanoscale FDSOI MOSFET Using Doped Silicon Tubs- A Simulation and Device Physics Based Study: Part II: Scalability to 10 nm Gate Length

TL;DR

This study uses simulation and device physics to analyze the scalability of doped silicon tub-based PWFDSOI MOSFETs to 10 nm gate length, achieving high ION/IOFF ratio and low subthreshold swing.

Contribution

It demonstrates the potential of doped silicon tubs in PWFDSOI MOSFETs for 10 nm scale with promising electrical characteristics.

Findings

Achieved ION/IOFF ratio of 7.6 x 10^5 at 10 nm gate length.

Obtained subthreshold swing of 87 mV/decade.

Confirmed device performance with unstrained silicon channel.

Abstract

The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET presented in this paper is on the scalability of the device to 10 nm gate length and its related information. A high ION /IOFF ratio of 7.6 x 10^5 and subthreshold swing of 87 mV/decade were achieved in 10 nm gate length PWFDSOI MOSFET. The study was performed on devices with unstrained silicon channel.