Insight into Potential Well Based Nanoscale FDSOI MOSFET Using Doped Silicon Tubs- A Simulation and Device Physics Based Study: Part I: Theory and Methodology

TL;DR

This paper introduces a novel potential well based FDSOI MOSFET with doped silicon tubs, demonstrating significant OFF current reduction and improved device performance through simulation and physics analysis.

Contribution

It presents a new device structure with doped silicon regions creating potential wells, leading to enhanced performance metrics at 20 nm gate length.

Findings

OFF current reduced by orders of magnitude

High ION/IOFF ratio of 1.5 x 10^7

Subthreshold swing of 76 mV/decade

Abstract

A novel planar device having doped silicon regions (tubs) under the source and drain of an FDSOI MOSFET is reported at 20 nm gate length. The doped silicon regions result in formation of potential wells (PW) in the source and drain regions of FDSOI MOSFET and thus, the device being called as Potential Well Based FDSOI MOSFET (PWFDSOI MOSFET). Simulation and device physics study on PWFDSOI MOSFET showed reduction in the OFF current of the device by orders of magnitude. A low IOF F of 22 pA/um, high ION /IOF F ratio of 1.5 x 107 and subthreshold swing of 76 mV/decade were achieved in 20 nm gate length PWFDSOI MOSFET. The study was performed on devices with unstrained silicon channel.