A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment

TL;DR

This paper introduces a machine learning pipeline stage that adaptively adjusts processor clock frequency based on instruction propagation delays, improving speed and energy efficiency.

Contribution

It presents a novel ML-based pipeline stage for real-time frequency adjustment, implemented in hardware and tested in a 45 nm CMOS processor.

Findings

70% speedup with 30% energy reduction at coarse granularity

89% speedup with 15.5% energy reduction at finer granularity

Effective real-time delay classification using random forest in hardware

Abstract

A machine learning (ML) design framework is proposed for adaptively adjusting clock frequency based on propagation delay of individual instructions. A random forest model is trained to classify propagation delays in real time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within a baseline processor. The modified system is experimentally tested at the gate level in 45 nm CMOS technology, exhibiting a speedup of 70% and energy reduction of 30% with coarse-grained ML classification. A speedup of 89% is demonstrated with finer granularities with 15.5% reduction in energy consumption.