Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption

TL;DR

This paper introduces an open-source hardware library and FPGA accelerator that significantly speeds up RLWE-based homomorphic encryption operations, enabling more efficient cryptographic computations.

Contribution

It presents the first hardware library for RLWE-based SHE operations, including a flexible, modular design and a high-speed FPGA implementation.

Findings

4200x faster homomorphic multiplication

2950x faster homomorphic addition

Flexible hardware design for encryption applications

Abstract

In this work, we propose an open-source, first-of-its-kind, arithmetic hardware library with a focus on accelerating the arithmetic operations involved in Ring Learning with Error (RLWE)-based somewhat homomorphic encryption (SHE). We design and implement a hardware accelerator consisting of submodules like Residue Number System (RNS), Chinese Remainder Theorem (CRT), NTT-based polynomial multiplication, modulo inverse, modulo reduction, and all the other polynomial and scalar operations involved in SHE. For all of these operations, wherever possible, we include a hardware-cost efficient serial and a fast parallel implementation in the library. A modular and parameterized design approach helps in easy customization and also provides flexibility to extend these operations for use in most homomorphic encryption applications that fit well into emerging FPGA-equipped cloud architectures. Using the submodules from the library, we prototype a hardware accelerator on FPGA. The evaluation of this hardware accelerator shows a speed up of approximately 4200x and 2950x to evaluate a homomorphic multiplication and addition respectively when compared to an existing software implementation.