Optimization of the surface code design for Majorana-based qubits

TL;DR

This paper develops optimized surface code error-correction schemes using only Pauli measurements, tailored for Majorana-based qubits, improving fault-tolerance and resource efficiency.

Contribution

It introduces new qubit layouts and measurement sequences for surface codes that do not rely on CNOT gates, specifically benefiting Majorana qubits.

Findings

Reduced logical error rates achieved

Enhanced fault-tolerance thresholds demonstrated

Trade-offs between qubit overhead and circuit depth analyzed

Abstract

The surface code is a prominent topological error-correcting code exhibiting high fault-tolerance accuracy thresholds. Conventional schemes for error correction with the surface code place qubits on a planar grid and assume native CNOT gates between the data qubits with nearest-neighbor ancilla qubits. Here, we present surface code error-correction schemes using $\textit{only}$ Pauli measurements on single qubits and on pairs of nearest-neighbor qubits. In particular, we provide several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree. We also develop minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds. Our work applies to topologically protected qubits realized with Majorana zero modes and to similar systems in which multi-qubit Pauli measurements rather than CNOT gates are the native operations.