A Compact Gated-Synapse Model for Neuromorphic Circuits

TL;DR

This paper introduces a compact, versatile behavioral model for gated-synaptic memory in neuromorphic circuits, implemented in Verilog-A, enabling easier integration and simulation of various gated synapse types.

Contribution

The work presents a unified, detailed behavioral model for gated synapses that can be integrated into neuromorphic circuit design, covering multiple synapse types within a single framework.

Findings

Model accurately fits experimental gated-synapse data

Enables simulation of diverse gated-synapse behaviors

Facilitates integration into neuromorphic circuit design

Abstract

This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated synapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters such as a device's ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the device's state, etc. Finally, the model's validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses.