Experimental observation and modeling of the impact of traps on static and analog/HF performance of graphene transistors

TL;DR

This paper investigates how traps affect the static and high-frequency performance of graphene transistors through experimental measurements and modeling, highlighting the importance of trap effects in device performance analysis.

Contribution

It introduces a practical measurement scheme to reduce hysteresis and develops an analytical model to study trap impacts on device performance.

Findings

Trap effects significantly influence high-frequency performance metrics.

Reproducible device characteristics are achieved using voltage pulse measurements.

Trap considerations are crucial for accurate modeling of graphene transistor behavior.

Abstract

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-free experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High-frequency figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and high-frequency applications.