Block-matching in FPGA

TL;DR

This paper presents an FPGA implementation of block-matching for the BM3D image denoising algorithm, enabling real-time video denoising in FPGA-based cameras by leveraging parallel computation capabilities.

Contribution

It introduces a novel FPGA-based block-matching implementation tailored for BM3D, facilitating real-time denoising applications.

Findings

Achieved real-time performance in FPGA for block-matching

Demonstrated suitability for video denoising in FPGA cameras

Enhanced computational efficiency through parallel processing

Abstract

Block-matching and 3D filtering (BM3D) is an image denoising algorithm that works in two similar steps. Both of these steps need to perform grouping by block-matching. We implement the block-matching in an FPGA, leveraging its ability to perform parallel computations. Our goal is to enable other researchers to use our solution in the future for real-time video denoising in video cameras that use FPGAs (such as the AXIOM Beta).