Spin Wave Normalization Towards all Magnonic Circuits

TL;DR

This paper introduces a novel energy-efficient spin wave (SW) gate cascading scheme using amplitude normalization via a directional coupler, enabling scalable, low-power magnonic circuits with significant energy savings over traditional methods.

Contribution

It proposes a conversion-free SW normalization scheme that improves energy efficiency and demonstrates its effectiveness through simple circuits and a 2-bit multiplier, validated by micromagnetic simulations.

Findings

Achieves 20-33% energy reduction compared to conventional transducer-based approaches.

Demonstrates 26% energy savings over traditional SW methods.

Shows 6.25x energy reduction compared to 16nm CMOS designs.

Abstract

The key enabling factor for Spin Wave (SW) technology utilization for building ultra low power circuits is the ability to energy efficiently cascade SW basic computation blocks. SW Majority gates, which constitute a universal gate set for this paradigm, operating on phase encoded data are not input output coherent in terms of SW amplitude, and as such, their cascading requires information representation conversion from SW to voltage and back, which is by no means energy effective. In this paper, a novel conversion free SW gate cascading scheme is proposed that achieves SW amplitude normalization by means of a directional coupler. After introducing the normalization concept, we utilize it in the implementation of three simple circuits and, to demonstrate its bigger scale potential, of a 2-bit inputs SW multiplier. The proposed structures are validated by means of the Object Oriented Micromagnetic Framework (OOMMF) and GPU-accelerated Micromagnetics (MuMax3). Furthermore, we assess the normalization induced energy overhead and demonstrate that the proposed approach consumes 20% to 33% less energy when compared with the transducers based conventional counterpart. Finally, we introduce a normalization based SW 2-bit inputs multiplier design and compare it with functionally equivalent SW transducer based and 16nm CMOS designs. Our evaluation indicate that the proposed approach provided 26% and 6.25x energy reductions when compared with the conventional approach and 16nm CMOS counterpart, respectively, which demonstrates that our proposal is energy effective and opens the road towards the full utilization of the SW paradigm potential and the development of SW only circuits.