A Faithful Binary Circuit Model with Adversarial Noise
Matthias F\"ugger, J\"urgen Maier, Robert Najvirt, Thomas, Nowak, Ulrich Schmid

TL;DR
This paper extends a faithful digital circuit delay model by incorporating limited non-deterministic variations, demonstrating that faithfulness is maintained and modeling power is increased, especially in handling glitch trains.
Contribution
It introduces a generalized involution delay model with controlled non-determinism, proving its faithfulness and enhanced modeling capabilities over previous deterministic models.
Findings
Faithfulness is preserved despite added non-determinism.
The generalized model better predicts real circuit behavior.
Small delay variations do not compromise model faithfulness.
Abstract
Accurate delay models are important for static and dynamic timing analysis of digital circuits, and mandatory for formal verification. However, F\"ugger et al. [IEEE TC 2016] proved that pure and inertial delays, which are employed for dynamic timing analysis in state-of-the-art tools like ModelSim, NC-Sim and VCS, do not yield faithful digital circuit models. Involution delays, which are based on delay functions that are mathematical involutions depending on the previous-output-to-input time offset, were introduced by F\"ugger et al. [DATE'15] as a faithful alternative (that can easily be used with existing tools). Although involution delays were shown to predict real signal traces reasonably accurately, any model with a deterministic delay function is naturally limited in its modeling power. In this paper, we thus extend the involution model, by adding non-deterministic delay…
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Taxonomy
TopicsIntegrated Circuits and Semiconductor Failure Analysis · VLSI and Analog Circuit Testing · Low-power high-performance VLSI design
