Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving

TL;DR

This paper introduces Binary DAD-Net, a binarized neural network for driveable area detection in autonomous driving, achieving high accuracy with minimal resource usage suitable for embedded systems.

Contribution

The paper presents a novel binarized network architecture for driveable area detection that reduces complexity and memory requirements while maintaining state-of-the-art performance.

Findings

Outperforms state-of-the-art segmentation networks on public datasets.

Achieves 14.3x reduction in compute complexity on FPGA.

Requires only 0.9MB memory resources.

Abstract

Driveable area detection is a key component for various applications in the field of autonomous driving (AD), such as ground-plane detection, obstacle detection and maneuver planning. Additionally, bulky and over-parameterized networks can be easily forgone and replaced with smaller networks for faster inference on embedded systems. The driveable area detection, posed as a two class segmentation task, can be efficiently modeled with slim binary networks. This paper proposes a novel binarized driveable area detection network (binary DAD-Net), which uses only binary weights and activations in the encoder, the bottleneck, and the decoder part. The latent space of the bottleneck is efficiently increased (x32 -> x16 downsampling) through binary dilated convolutions, learning more complex features. Along with automatically generated training data, the binary DAD-Net outperforms state-of-the-art semantic segmentation networks on public datasets. In comparison to a full-precision model, our approach has a x14.3 reduced compute complexity on an FPGA and it requires only 0.9MB memory resources. Therefore, commodity SIMD-based AD-hardware is capable of accelerating the binary DAD-Net.