A Unified Learning Platform for Dynamic Frequency Scaling in Pipelined Processors

TL;DR

This paper presents a machine learning-based framework for dynamically adjusting processor clock frequency to optimize speed and energy efficiency, using a Random Forest model integrated into a pipelined processor.

Contribution

It introduces a unified platform that employs ML for real-time frequency scaling in pipelined processors, demonstrating significant performance and energy improvements.

Findings

68% speed-up and 37% energy reduction with coarse classification

95% speed-up with finer granularity at higher energy cost

Implemented in Verilog and simulated in 45 nm CMOS technology

Abstract

A machine learning (ML) design framework is proposed for dynamically adjusting clock frequency based on propagation delay of individual instructions. A Random Forest model is trained to classify propagation delays in real-time, utilizing current operation type, current operands, and computation history as ML features. The trained model is implemented in Verilog as an additional pipeline stage within a baseline processor. The modified system is simulated at the gate-level in 45 nm CMOS technology, exhibiting a speed-up of 68% and energy reduction of 37% with coarse-grained ML classification. A speed-up of 95% is demonstrated with finer granularities at additional energy costs.