Stochastic Automata Network for Performance Evaluation of Heterogeneous SoC Communication

TL;DR

This paper introduces a modular stochastic automata network model for early performance evaluation of bus-based communication architectures in heterogeneous SoC systems, aiding design optimization.

Contribution

It presents a novel modeling methodology using SAN and GSMP to accurately estimate key performance metrics of SoC communication architectures early in design.

Findings

Provides estimates of memory bandwidth and queue lengths

Models dynamic behavior of processing elements effectively

Enables early performance assessment to optimize design choices

Abstract

To meet ever increasing demand for performance of emerging System-on-Chip (SoC) applications, designer employ techniques for concurrent communication between components. Hence communication architecture becomes complex and major performance bottleneck. An early performance evaluation of communication architecture is the key to reduce design time, time-to-market and consequently cost of the system. Moreover, it helps to optimize system performance by selecting appropriate communication architecture. However, performance model of concurrent communication is complex to describe and hard to solve. In this paper, we propose methodology for performance evaluation of bus based communication architectures, modeling for which is based on modular Stochastic Automata Network (SAN). We employ Generalized Semi Markov Process (GSMP) model for each module of the SAN that emulates dynamic behavior of a Processing Element (PE) of an SoC architecture. The proposed modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element; while we provide parameters viz. number of processing elements, the mean computation time of processing elements and the first and second moments of connection time between processing elements and memories, as input to the model.