Improving performance of logical qubits by parameter tuning and topology compensation

TL;DR

This paper enhances quantum annealing performance by optimizing minor-embedding parameters and topology compensation, improving the accuracy of logical qubit representations on D-Wave quantum hardware.

Contribution

It introduces parameter tuning protocols and topology compensation techniques for logical qubits in quantum annealing, specifically addressing inhomogeneities in coupling strengths.

Findings

Parameter tuning improves annealing results in spin glasses and communication problems.

Topology compensation mitigates inhomogeneity effects in logical qubits.

Reweighting couplings enhances logical qubit fidelity.

Abstract

Optimization or sampling of arbitrary pairwise Ising models, in a quantum annealing protocol of constrained interaction topology, can be enabled by a minor-embedding procedure. The logical problem of interest is transformed to a physical (device programmable) problem, where one binary variable is represented by a logical qubit consisting of multiple physical qubits. In this paper we discuss tuning of this transformation for the cases of clique, biclique, and cubic lattice problems on the D-Wave 2000Q quantum computer. We demonstrate parameter tuning protocols in spin glasses and channel communication problems, focusing on anneal duration, chain strength, and mapping from the result on physical qubits back to the logical space. Inhomogeneities in effective coupling strength arising from minor-embedding are shown to be mitigated by an efficient reweighting of programmed couplings, accounting for logical qubit topology.