High-level Modeling of Manufacturing Faults in Deep Neural Network Accelerators

TL;DR

This paper presents a formal probabilistic model of manufacturing faults in TPU neural network accelerators, analyzing their impact on classification accuracy through model checking and experimental validation.

Contribution

It introduces a formal DTMC-based model for permanent faults in TPU hardware and analyzes their effect on DNN inference accuracy.

Findings

Fault type and location significantly affect accuracy

Model checking quantifies fault impact probabilities

Experimental validation confirms theoretical predictions

Abstract

The advent of data-driven real-time applications requires the implementation of Deep Neural Networks (DNNs) on Machine Learning accelerators. Google's Tensor Processing Unit (TPU) is one such neural network accelerator that uses systolic array-based matrix multiplication hardware for computation in its crux. Manufacturing faults at any state element of the matrix multiplication unit can cause unexpected errors in these inference networks. In this paper, we propose a formal model of permanent faults and their propagation in a TPU using the Discrete-Time Markov Chain (DTMC) formalism. The proposed model is analyzed using the probabilistic model checking technique to reason about the likelihood of faulty outputs. The obtained quantitative results show that the classification accuracy is sensitive to the type of permanent faults as well as their location, bit position and the number of layers in the neural network. The conclusions from our theoretical model have been validated using experiments on a digit recognition-based DNN.