Strategies for on-chip digital data compression for X-ray pixel detectors

TL;DR

This paper introduces innovative on-chip data compression strategies for X-ray pixel detectors, significantly enhancing off-chip bandwidth efficiency and enabling higher frame rates in X-ray imaging applications.

Contribution

It presents a novel in-pixel compression scheme and a zero-suppression method, both implemented in 65-nm CMOS, to improve data throughput for high-speed X-ray detectors.

Findings

In-pixel compression achieves >1.5× ratio near Poisson noise level.

Zero-mask compression yields >4× to >8× ratios for various datasets.

Combined schemes could increase bandwidth by 6-12×.

Abstract

The continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of $>\!1.5\times$ independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called ``zeromask'' (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of $>\!4\times$, $>\!7\times$, and $>\!8\times$ for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65-nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12$\times$.