Operation Merging for Hardware Implementations of Fast Polar Decoders
Furkan Ercan, Thibaud Tonnellier, Carlo Condo, Warren J. Gross

TL;DR
This paper introduces a novel Fast-SSC decoder architecture for polar codes that reduces memory usage and operation steps, significantly improving throughput for 5G communication systems.
Contribution
It proposes new special node merging techniques and a decoder architecture that enhances decoding speed and efficiency over previous Fast-SSC methods.
Findings
Operation sequence reduced by up to 39%
Decoding time steps decreased by 35%
Throughput increased by up to 31% in ASIC implementation
Abstract
Polar codes are a class of linear block codes that provably achieves channel capacity. They have been selected as a coding scheme for the control channel of enhanced mobile broadband (eMBB) scenario for generation wireless communication networks (5G) and are being considered for additional use scenarios. As a result, fast decoding techniques for polar codes are essential. Previous works targeting improved throughput for successive-cancellation (SC) decoding of polar codes are semi-parallel implementations that exploit special maximum-likelihood (ML) nodes. In this work, we present a new fast simplified SC (Fast-SSC) decoder architecture. Compared to a baseline Fast-SSC decoder, our solution is able to reduce the memory requirements. We achieve this through a more efficient memory utilization, which also enables to execute multiple operations in a single clock cycle.…
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