CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism

TL;DR

This paper introduces Clarinet, a RISC-V based framework with a novel posit arithmetic core called Melodica, enabling validation and experimentation of posit arithmetic's advantages over floating-point in scientific computing.

Contribution

It presents the first integration of posit quire with a RISC-V processor, providing an open-source platform for posit arithmetic validation and benchmarking.

Findings

Effective emulation on FPGA demonstrates practical viability.

Benchmark results show competitive performance in linear algebra and vision kernels.

Framework supports seamless experimentation with posit and floating-point arithmetic.

Abstract

Many engineering and scientific applications require high precision arithmetic. IEEE~754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these computations. Recently, posit arithmetic has been proposed as a drop-in replacement for floating-point arithmetic. The posit\texttrademark data representation and arithmetic claim several absolute advantages over the floating-point format and arithmetic, including higher dynamic range, better accuracy, and superior performance-area trade-offs. However, there does not exist any accessible, holistic framework that facilitates the validation of these claims of posit arithmetic, especially when the claims involve long accumulations (quire). In this paper, we present a consolidated general-purpose processor-based framework to support posit arithmetic empiricism. The end-users of the framework have the liberty to seamlessly experiment with their applications using posit and floating-point arithmetic since the framework is designed for the two number systems to coexist. Melodica is a posit arithmetic core that implements parametric fused operations that uniquely involve the quire data type. Clarinet is a Melodica-enabled processor based on the RISC-V ISA. To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core. To show the effectiveness of the Clarinet platform, we perform an extensive application study and benchmark some of the common linear algebra and computer vision kernels. We emulate Clarinet on a Xilinx FPGA and present utilization and timing data. Clarinet and Melodica remain actively under development and is available in open-source for posit arithmetic empiricism.