3D logic cells design and results based on Vertical NWFET technology including tied compact model

TL;DR

This paper presents a detailed design and simulation of 3D logic cells using Vertical NWFET technology, including a compact model that accurately predicts device behavior and demonstrates potential for scaled, compact logic circuits.

Contribution

It introduces a compact model for junctionless vertical nanowire FETs and demonstrates a 1.4x reduction in lateral dimensions compared to 7nm FinFETs.

Findings

Accurate device behavior modeling across all operational regions.

Projected inverter performance based on various nanowire configurations.

Significant size reduction in logic cell layout compared to existing FinFET technology.

Abstract

Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and carry out an performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 1.4x reduction in lateral dimensions for the complementary structure with respect to 7nm FinFET-based inverters.