Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

TL;DR

This paper experimentally analyzes how modern DRAM chips are increasingly vulnerable to RowHammer attacks as technology advances, and evaluates the scalability of current mitigation techniques, highlighting the need for more effective solutions.

Contribution

It provides a comprehensive experimental characterization of RowHammer across various modern DRAM chips and assesses the scalability of existing mitigation methods.

Findings

Newer DRAM chips are more vulnerable to RowHammer.

Fewer activations are needed to induce bit flips in advanced chips.

Current mitigation techniques are not scalable for future DRAM devices.

Abstract

In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4, and 520x LPDDR4) from 300 DRAM modules (60x DDR3, 110x DDR4, and 130x LPDDR4) with RowHammer protection mechanisms disabled, spanning multiple different technology nodes from across each of the three major DRAM manufacturers. Our studies definitively show that newer DRAM chips are more vulnerable to RowHammer: as device feature size reduces, the number of activations needed to induce a RowHammer bit flip also reduces, to as few as 9.6k (4.8k to two rows each) in the most vulnerable chip we tested. We evaluate five state-of-the-art RowHammer mitigation mechanisms using cycle-accurate simulation in the context of real data taken from our chips to study how the mitigation mechanisms scale with chip vulnerability. We find that existing mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices given our observed trends of RowHammer vulnerability. Thus, it is critical to research more effective solutions to RowHammer.