Characterization of an architecture for front-end pixel binning in an integrating pixel array detector
D. Gadkari, K.S. Shanks, H.T. Philipp, M.W. Tate, J. Thom-Levy, S.M., Gruner

TL;DR
This paper presents a novel front-end pixel binning architecture for hybrid pixel array detectors, enabling a trade-off between spatial resolution and frame rate, with tested performance showing promising results and areas for improvement.
Contribution
The paper introduces and characterizes a new front-end binning design in an integrating pixel detector, demonstrating its performance and potential benefits over traditional post-processing binning.
Findings
Binned pixels perform well with some performance degradation.
Noise increase due to parasitic capacitance is less than a factor of 2.
Binned mode maintains linear response up to ~10^7 x-rays/s.
Abstract
Optimization of an area detector involves compromises between various parameters like frame rate, read noise, dynamic range and pixel size. We have implemented and tested a novel front-end binning design in a photon-integrating hybrid pixel array detector using the MM-PAD-2.0 pixel architecture. In this architecture, the pixels can be optionally binned in a 22 pixel configuration using a network of switches to selectively direct the output of 4 sensor pixels to a single amplifier input. Doing this allows a trade-off between frame rate and spatial resolution. Tests show that the binned pixels perform well, but with some degradation on performance as compared to an un-binned pixel. The increased parasitic input capacitance does reduce the signal collected per x-ray as well as increases the noise of the pixel. The increase in noise is, however, less than the factor of 2 increase…
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