Latch-Based Logic Locking

TL;DR

This paper introduces latch-based logic locking, a security technique that modifies flip-flops with programmable phase and adds decoy elements, providing strong protection against attacks with lower overhead than previous methods.

Contribution

It presents a novel latch-based logic locking method that reduces overhead and enhances resistance to deciphering attacks compared to existing techniques.

Findings

Significantly lower design overhead than previous schemes

Resists model checker-based and oracle-driven attacks

Can incorporate many decoy latches with minimal delay impact

Abstract

Globalization of IC manufacturing has led to increased security concerns, notably IP theft. Several logic locking techniques have been developed for protecting designs, but they typically display very large overhead, and are generally susceptible to deciphering attacks. In this paper, we propose latch-based logic locking, which manipulates both the flow of data and logic in the design. This method converts an interconnected subset of existing flip-flops to pairs of latches with programmable phase. In tandem, decoy latches and logic are added, inhibiting an attacker from determining the actual design functionality. To validate this technique, we developed and verified a locking insertion flow, analyzed PPA and ATPG overhead on benchmark circuits and industry cores, extended existing attacks to account for the technique, and taped out a demonstration chip. Importantly, we show that the design overhead with this approach is significantly less than with previous logic locking schemes, while resisting model checker-based, oracle-driven attacks. With minimal delay overhead, large numbers of decoy latches can be added, cheaply increasing attack resistance.