Securing Digital Systems via Split-Chip Obfuscation

TL;DR

This paper introduces Split-Chip Obfuscation, a method combining trusted and untrusted fabrication processes to enhance security in integrated circuits, supported by a new design flow and assessment tool.

Contribution

It develops a novel design flow and a rapid assessment tool for optimal partitioning in Split-Chip Obfuscation, improving security in IC fabrication.

Findings

Effective partitioning strategies identified

Design flow and tool demonstrated on example SoC

Enhanced security with combined CMOS processes

Abstract

Security is an important facet of integrated circuit design for many applications. IP privacy and Trojan insertion are growing threats as circuit fabrication in advanced nodes almost inevitably relies on untrusted foundries. A proposed solution is Split-Chip Obfuscation that uses a combination trusted and untrusted IC fabrication scheme. By utilizing two CMOS processes, a system is endowed with the stronger security guaranties of a trusted legacy node while also leveraging the performance and density of an advanced untrusted node. Critical to the effectiveness of Split-Chip Obfuscation is finding an optimum partitioning of a system between the two ICs. In this paper, we develop a design flow for the Split-Chip Obfuscation scheme, defining the essential system metrics and creating a tool to rapidly assess the large design space. We demonstrate the concept of such a tool and show its application on an example SoC.