Spin readout of a CMOS quantum dot by gate reflectometry and spin-dependent tunnelling

TL;DR

This paper demonstrates a CMOS-compatible silicon quantum dot device capable of electron spin readout using gate reflectometry and spin-dependent tunneling, achieving long spin relaxation times suitable for scalable quantum computing.

Contribution

It introduces a CMOS-compatible fabrication process for silicon quantum dots with effective spin readout and long spin relaxation times, advancing scalable quantum processor development.

Findings

Achieved spin readout using gate reflectometry and spin-dependent tunneling.

Measured valley splittings of 0.5-0.7 meV.

Observed electron spin relaxation times up to 9 seconds.

Abstract

Silicon spin qubits are promising candidates for realising large scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly-occupied gate-defined quantum dot, fabricated using CMOS compatible processes at the 300 mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum dot charge sensor, measured using radiofrequency gate reflectometry. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5-0.7 meV using excited state spectroscopy, and measure a maximum electron spin relaxation time ($T_1$) of $9 \pm 3$ s at 1 Tesla. These long lifetimes indicate the silicon nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices, while the spin-readout method demonstrated here is well-suited to a variety of scalable architectures.