Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS$_2$ FETs
Himani Jawa, Abin Varghese, and Saurabh Lodha

TL;DR
This study demonstrates room temperature hysteresis crossover in MoS2 FETs using an underlap design, enabling tunable hysteresis characteristics for potential non-volatile memory applications.
Contribution
First demonstration of room temperature hysteresis crossover in MoS2 FETs via a gate-drain underlap design that modulates interface traps.
Findings
Room temperature hysteresis crossover achieved in MoS2 FETs.
Hysteresis window and crossover voltage can be tuned by device parameters.
Interface traps and adsorbates significantly influence hysteresis behavior.
Abstract
Clockwise to anti-clockwise hysteresis crossover in current-voltage transfer characteristics of field effect transistors (FETs) with graphene and MoS channels holds significant promise for non-volatile memory applications. However such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS FETs by using a gate-drain underlap design to induce a differential response from traps at the MoS-HfO channel-gate dielectric interface to applied gate bias. The appearance of interface trap-driven anti-clockwise hysteresis at high gate voltages in underlap FETs can be unambiguously attributed to the presence of an underlap since transistors with and without the underlap region were fabricated on the same MoS channel flake. The underlap design also enables room…
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Taxonomy
TopicsSemiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and interfaces
