Performance Limit and Coding Schemes for Resistive Random-Access Memory Channels

TL;DR

This paper introduces a novel coding strategy for ReRAM channels that mitigates sneak-path interference and noise, leveraging across-array coding and real-time channel estimation to approach the channel capacity.

Contribution

It proposes an across-array coding scheme with real-time channel estimation to combat data-dependent interference in ReRAM, achieving near-capacity storage efficiency.

Findings

The coding scheme effectively mitigates sneak-path interference.

Achieves near-capacity storage efficiency.

Provides capacity bounds for the ReRAM channel.

Abstract

Resistive random-access memory (ReRAM) is a promising candidate for the next generation non-volatile memory technology due to its simple read/write operations and high storage density. However, its crossbar array structure causes a severe interference effect known as the "sneak path." In this paper, we propose channel coding techniques that can mitigate both the sneak-path interference and the channel noise. The main challenge is that the sneak-path interference is data-dependent, and also correlated within a memory array, and hence the conventional error correction coding scheme will be inadequate. In this work, we propose an across-array coding strategy that assigns a codeword to multiple independent memory arrays, and exploit a real-time channel estimation scheme to estimate the instantaneous status of the ReRAM channel. Since the coded bits from different arrays experience independent channels, a "diversity" gain can be obtained during decoding, and when the codeword is adequately distributed over different memory arrays, the code actually performs as that over an uncorrelated channel. By performing decoding based on the scheme of treating-interference-as-noise (TIN), the ReRAM channel over different memory arrays is equivalent to a block varying channel we defined, for which we propose both the capacity bounds and a coding scheme. The proposed coding scheme consists of a serial concatenation of an optimized error correction code with a data shaper, which enables the ReRAM system to achieve a near capacity limit storage efficiency.