Nonlinear analysis of charge-pump phase-locked loop: the hold-in and pull-in ranges
N.V. Kuznetsov, A.S. Matveev, M.V. Yuldashev, R.V. Yuldashev

TL;DR
This paper develops a comprehensive mathematical model of charge-pump phase-locked loops (CP-PLLs) to analyze their stability, hold-in, and pull-in ranges, addressing nonlinear dynamics and confirming longstanding conjectures.
Contribution
It refines stability definitions, provides a detailed local stability analysis, computes the hold-in range, estimates the pull-in range, and resolves key conjectures in CP-PLL dynamics.
Findings
Computed the hold-in range for CP-PLL.
Provided an upper estimate of the pull-in range.
Confirmed conjectures on the similarity of transient responses and infinite pull-in range.
Abstract
In this paper a fairly complete mathematical model of CP-PLL, which reliable enough to serve as a tool for credible analysis of dynamical properties of these circuits, is studied. We refine relevant mathematical definitions of the hold-in and pull-in ranges related to the local and global stability. Stability analysis of the steady state for the charge-pump phase locked loop is non-trivial: straight-forward linearization of available CP-PLL models may lead to incorrect conclusions, because the system is not smooth near the steady state and may experience overload. In this work necessary details for local stability analysis are presented and the hold-in range is computed. An upper estimate of the pull-in range is obtained via the analysis of limit cycles. The study provided an answer to Gardner's conjecture on the similarity of transient responses of CP-PLL and equivalent classical PLL…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdvancements in PLL and VCO Technologies · Low-power high-performance VLSI design · Analog and Mixed-Signal Circuit Design
