GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

TL;DR

This paper introduces GCN-RL Circuit Designer, a method combining graph neural networks and reinforcement learning to transfer transistor sizing knowledge across different circuits and technology nodes, improving design efficiency.

Contribution

It presents a novel transferable optimization approach using GCN and RL, enabling effective knowledge transfer in transistor sizing across circuits and technology nodes.

Findings

Achieves highest Figures of Merit compared to traditional methods.

Transfer learning significantly improves optimization across technology nodes.

Effective in multiple circuit topologies.

Abstract

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.