Synergistic CPU-FPGA Acceleration of Sparse Linear Algebra

TL;DR

This paper presents REAP, a cooperative CPU-FPGA system that significantly accelerates sparse linear algebra operations by dividing tasks between CPU and FPGA, optimizing data organization and computation.

Contribution

The paper introduces a novel software-hardware approach with a new intermediate representation for efficient sparse matrix processing on CPU-FPGA platforms.

Findings

REAP achieves 3.2X speedup for SpGEMM

REAP achieves 1.85X speedup for Sparse Cholesky

Enhanced resource utilization through pipelined FPGA computation

Abstract

This paper describes REAP, a software-hardware approach that enables high performance sparse linear algebra computations on a cooperative CPU-FPGA platform. REAP carefully separates the task of organizing the matrix elements from the computation phase. It uses the CPU to provide a first-pass re-organization of the matrix elements, allowing the FPGA to focus on the computation. We introduce a new intermediate representation that allows the CPU to communicate the sparse data and the scheduling decisions to the FPGA. The computation is optimized on the FPGA for effective resource utilization with pipelining. REAP improves the performance of Sparse General Matrix Multiplication (SpGEMM) and Sparse Cholesky Factorization by 3.2X and 1.85X compared to widely used sparse libraries for them on the CPU, respectively.