Hardware Memory Management for Future Mobile Hybrid Memory Systems
Fei Wen, Mian Qin, Paul Gratz, Narasimha Reddy

TL;DR
This paper introduces a hardware-accelerated memory manager for future mobile systems that combines DRAM and NVM to optimize performance, energy, and endurance, addressing the limitations of each memory type.
Contribution
It proposes a novel HMMU with data placement and migration policies to effectively integrate DRAM and NVM in a flat address space.
Findings
39% reduction in energy consumption
12% performance degradation
Effective exploitation of memory technologies
Abstract
The current mobile applications have rapidly growing memory footprints, posing a great challenge for memory system design. Insufficient DRAM main memory will incur frequent data swaps between memory and storage, a process that hurts performance, consumes energy and deteriorates the write endurance of typical flash storage devices. Alternately, a larger DRAM has higher leakage power and drains the battery faster. Further, DRAM scaling trends make further growth of DRAMin the mobile space prohibitive due to cost. Emerging non-volatile memory (NVM) has the potential to alleviate these issues due to its higher capacity per cost than DRAM and mini-mal static power. Recently, a wide spectrum of NVM technologies, including phase-change memories (PCM), memristor, and 3D XPoint have emerged. Despite the mentioned advantages, NVM has longer access latency compared to DRAMand NVM writes can incur…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Parallel Computing and Optimization Techniques · Caching and Content Delivery
