DNN-aided Read-voltage Threshold Optimization for MLC Flash Memory with Finite Block Length

TL;DR

This paper proposes a DNN-assisted method to optimize read-voltage thresholds in MLC flash memory, enhancing error correction performance, endurance, and reducing latency by addressing the challenges of data retention noise.

Contribution

It introduces a deep neural network-based approach for read-voltage threshold optimization, overcoming the difficulty of modeling voltage distribution under retention noise.

Findings

Improved decoding error probability with optimized thresholds.

Enhanced program-and-erase endurance.

Reduced read latency in flash memory operations.

Abstract

The error correcting performance of multi-level-cell (MLC) NAND flash memory is closely related to the block length of error correcting codes (ECCs) and log-likelihood-ratios (LLRs) of the read-voltage thresholds. Driven by this issue, this paper optimizes the read-voltage thresholds for MLC flash memory to improve the decoding performance of ECCs with finite block length. First, through the analysis of channel coding rate (CCR) and decoding error probability under finite block length, we formulate the optimization problem of read-voltage thresholds to minimize the maximum decoding error probability. Second, we develop a cross iterative search (CIS) algorithm to optimize read-voltage thresholds under the perfect knowledge of flash memory channel. However, it is challenging to analytically characterize the voltage distribution under the effect of data retention noise (DRN), since the data retention time (DRT) is hard to be recorded for flash memory in reality. To address this problem, we develop a deep neural network (DNN) aided optimization strategy to optimize the read-voltage thresholds, where a multi-layer perception (MLP) network is employed to learn the relationship between voltage distribution and read-voltage thresholds. Simulation results show that, compared with the existing schemes, the proposed DNN-aided read-voltage threshold optimization strategy with a well-designed LDPC code can not only improve the program-and-erase (PE) endurance but also reduce the read latency.