$MC^2RAM$: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference

TL;DR

This paper introduces a novel SRAM-based architecture for high-speed MCMC sampling of Gaussian mixture models, integrating RNGs, DACs, and ADCs to enable parallel, low-power Bayesian inference.

Contribution

It presents a new SRAM design embedding analog and digital components for efficient MCMC sampling, reducing data movement and improving speed and power efficiency.

Findings

Consumes ~91 micro-Watts per sample at 1 GHz

Generates 500 samples in 2000 cycles

Highlights impact of hardware non-idealities on sampling quality

Abstract

This work discusses the implementation of Markov Chain Monte Carlo (MCMC) sampling from an arbitrary Gaussian mixture model (GMM) within SRAM. We show a novel architecture of SRAM by embedding it with random number generators (RNGs), digital-to-analog converters (DACs), and analog-to-digital converters (ADCs) so that SRAM arrays can be used for high performance Metropolis-Hastings (MH) algorithm-based MCMC sampling. Most of the expensive computations are performed within the SRAM and can be parallelized for high speed sampling. Our iterative compute flow minimizes data movement during sampling. We characterize power-performance trade-off of our design by simulating on 45 nm CMOS technology. For a two-dimensional, two mixture GMM, the implementation consumes ~ 91 micro-Watts power per sampling iteration and produces 500 samples in 2000 clock cycles on an average at 1 GHz clock frequency. Our study highlights interesting insights on how low-level hardware non-idealities can affect high-level sampling characteristics, and recommends ways to optimally operate SRAM within area/power constraints for high performance sampling.