Binary Representaion for Non-binary LDPC Code with Decoder Design

TL;DR

This paper introduces a method to transform non-binary LDPC codes into cycle-free binary forms, improving decoding performance and complexity through novel code structures and hybrid decoders.

Contribution

It proposes an extended p-reducible (EPR) LDPC code structure to eliminate bit-level cycles and introduces hybrid decoders for enhanced decoding efficiency.

Findings

EPR-LDPC codes reduce short cycle effects

Hybrid decoders improve decoding performance

Proposed methods lower decoding complexity

Abstract

The equivalent binary parity check matrices for the binary images of the cycle-free non-binary LDPC codes have numerous bit-level cycles. In this paper, we show how to transform these binary parity check matrices into their cycle-free forms. It is shown that the proposed methodology can be adopted not only for the binary images of non-binary LDPC codes but also for a large class of binary LDPC codes. Specifically, we present an extended $p$-reducible (EPR) LDPC code structure to eliminate the bit-level cycles. For the non-binary LDPC codes with short length symbol-level cycles, the EPR-LDPC codes can largely avoid the corresponding short length bit-level cycles. As to the decoding of the EPR-LDPC codes, we propose a hybrid hard-decision decoder and a hybrid parallel decoder for binary symmetric channel and binary input Gaussian channel, respectively. A simple code optimization algorithm for these binary decoders is also provided. Simulations show the comparative results and justify the advantages, i.e., better performance and lower decoding complexity, of the proposed binary constructions.