Hierarchical decoding to reduce hardware requirements for quantum computing

TL;DR

This paper introduces a hierarchical decoding architecture for quantum error correction that significantly reduces hardware requirements and improves decoding speed, making scalable quantum computing more feasible with current and near-future qubits.

Contribution

It proposes a fault-tolerant quantum computing architecture utilizing a lazy hard-decision decoder combined with complex error decoding, drastically reducing hardware needs.

Findings

50x reduction in bandwidth and hardware with p=10^{-4} qubits

1500x reduction in hardware with p=10^{-5} qubits

10x to 50x speed-up in decoder performance

Abstract

Extensive quantum error correction is necessary in order to scale quantum hardware to the regime of practical applications. As a result, a significant amount of decoding hardware is necessary to process the colossal amount of data required to constantly detect and correct errors occurring over the millions of physical qubits driving the computation. The implementation of a recent highly optimized version of Shor's algorithm to factor a 2,048-bits integer would require more 7 TBit/s of bandwidth for the sole purpose of quantum error correction and up to 20,000 decoding units. To reduce the decoding hardware requirements, we propose a fault-tolerant quantum computing architecture based on surface codes with a cheap hard-decision decoder, the lazy decoder, combined with a sophisticated decoding unit that takes care of complex error configurations. Our design drops the decoding hardware requirements by several orders of magnitude assuming that good enough qubits are provided. Given qubits and quantum gates with a physical error rate $p=10^{-4}$, the lazy decoder drops both the bandwidth requirements and the number of decoding units by a factor 50x. Provided very good qubits with error rate $p=10^{-5}$, we obtain a 1,500x reduction in bandwidth and decoding hardware thanks to the lazy decoder. Finally, the lazy decoder can be used as a decoder accelerator. Our simulations show a 10x speed-up of the Union-Find decoder and a 50x speed-up of the Minimum Weight Perfect Matching decoder.