Development, Demonstration, and Validation of Data-driven Compact Diode Models for Circuit Simulation and Analysis
K. Aadithya, P. Kuberry, B. Paskaleva, P. Bochev, K. Leeson, A. Mar,, T. Mei, E. Keiter

TL;DR
This paper explores machine learning techniques to develop data-driven compact diode models, aiming to automate and accelerate the modeling process while maintaining accuracy for circuit simulation and analysis.
Contribution
It introduces three ML-based modeling approaches for diodes and validates their effectiveness through circuit simulation comparisons with laboratory data.
Findings
ML models accurately predict diode I-V characteristics
Data-driven models successfully simulate circuit behavior
Approaches reduce development time compared to traditional methods
Abstract
Compact semiconductor device models are essential for efficiently designing and analyzing large circuits. However, traditional compact model development requires a large amount of manual effort and can span many years. Moreover, inclusion of new physics (eg, radiation effects) into an existing compact model is not trivial and may require redevelopment from scratch. Machine Learning (ML) techniques have the potential to automate and significantly speed up the development of compact models. In addition, ML provides a range of modeling options that can be used to develop hierarchies of compact models tailored to specific circuit design stages. In this paper, we explore three such options: (1) table-based interpolation, (2)Generalized Moving Least-Squares, and (3) feed-forward Deep Neural Networks, to develop compact models for a p-n junction diode. We evaluate the performance of these…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdvancements in Semiconductor Devices and Circuit Design · VLSI and FPGA Design Techniques · VLSI and Analog Circuit Testing
MethodsSPEED: Separable Pyramidal Pooling EncodEr-Decoder for Real-Time Monocular Depth Estimation on Low-Resource Settings
