Structural plasticity on an accelerated analog neuromorphic hardware system

TL;DR

This paper introduces a structural plasticity strategy implemented on the BrainScaleS-2 neuromorphic hardware, enabling dynamic rewiring to optimize network topology within hardware constraints, demonstrated through a supervised learning task.

Contribution

It presents a novel algorithm for structural plasticity that dynamically rewires connections on neuromorphic hardware, improving resource utilization and network adaptability.

Findings

Successfully implemented on BrainScaleS-2 hardware

Enhanced network topology optimization during supervised learning

Demonstrated improved computational efficiency

Abstract

In computational neuroscience, as well as in machine learning, neuromorphic devices promise an accelerated and scalable alternative to neural network simulations. Their neural connectivity and synaptic capacity depends on their specific design choices, but is always intrinsically limited. Here, we present a strategy to achieve structural plasticity that optimizes resource allocation under these constraints by constantly rewiring the pre- and gpostsynaptic partners while keeping the neuronal fan-in constant and the connectome sparse. In particular, we implemented this algorithm on the analog neuromorphic system BrainScaleS-2. It was executed on a custom embedded digital processor located on chip, accompanying the mixed-signal substrate of spiking neurons and synapse circuits. We evaluated our implementation in a simple supervised learning scenario, showing its ability to optimize the network topology with respect to the nature of its training data, as well as its overall computational efficiency.