SSR: A Stall Scheme Reducing Bubbles in Load-Use Hazard of RISC-V Pipeline

TL;DR

This paper proposes a bypass scheme in RISC-V pipelines that reduces bubbles caused by load-use hazards, leading to a 6.9% performance improvement in benchmarks with minimal additional cost.

Contribution

A novel bypass scheme between EXE and MEM stages that effectively reduces pipeline stalls due to load-use hazards in RISC-V processors.

Findings

Performance increased by 6.9% in Dhrystone benchmark.

Significant reduction of pipeline bubbles in load-use hazard scenarios.

Implementation in Rocket-chip shows practical viability.

Abstract

Modern processors usually adopt pipeline structure and often load data from memory. At that point, the load-use hazard will inevitably occur, which usually stall the pipeline and reduce performance. This paper introduces and compares two schemes to solve load-use hazard. One is the traditional scheme that detect hazard between ID stage and EXE stage, which stalls the pipeline and insert bubbles between the two instructions. In the scheme we proposed, we add a simple bypass unit between EXE and MEM stage that disables the stall of load-use hazard caused by the traditional scheme, which can reduce the bubble between the two instructions. It's quite a considerable benefit in eliminating bubbles especially in the long pipeline or programs of plenty load instructions. The scheme was implemented in the open source RISC-V SoC generator Rocket-chip and synthesized in SMIC 130-nm technology. The results show that the performance of the latter scheme is increased by 6.9% in the Dhrystone benchmark with the reasonable cost of area and power.