Automated Deductive Verification for Ladder Programming
Denis Cousineau (Mitsubishi Electric R&D Centre Europe (MERCE) Rennes,, France), David Mentr\'e (Mitsubishi Electric R&D Centre Europe (MERCE), Rennes, France), Hiroaki Inoue (Mitsubishi Electric Corporation Amagasaki,, Japan)

TL;DR
This paper introduces a tool that automates deductive verification for Ladder Logic programs, aiming to improve debugging efficiency and robustness in industrial PLC programming.
Contribution
The paper presents a novel, automated deductive verification tool based on Why3 for Ladder Logic, enhancing debugging processes for industrial PLC programs.
Findings
Automated verification reduces debugging time.
Improves robustness of Ladder Logic programs.
Provides a user-friendly debugging tool.
Abstract
Ladder Logics is a programming language standardized in IEC 61131-3 and widely used for programming industrial Programmable Logic Controllers (PLC). A PLC program consists of inputs (whose values are given at runtime by factory sensors), outputs (whose values are given at runtime to factory actuators), and the logical expressions computing output values from input values. Due to the graphical form of Ladder programs, and the amount of inputs and outputs in typical industrial programs, debugging such programs is time-consuming and error-prone. We present, in this paper, a Why3-based tool prototype we have implemented for automating the use of deductive verification in order to provide an easy-to-use and robust debugging tool for Ladder programmers.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
